The present invention relates generally to high frequency memory, and more specifically, to high frequency write through memory.
In general, a write policy determines how a memory device performs a write operation. One common write policy is a called a write through policy. In a memory device having a write through policy, the processor writes through the memory device to another location, such as the main memory. During the write though, the memory device may update its contents, but the write operation is not complete until the data is passed though the memory device to the other location. Currently available memory devices that have a write-though policies are generally configured to be able to perform both write though data operations and read operations.
High frequency circuit design requires the use of short, or narrow, evaluation pulses as well as short restore pulses. Accordingly, in order to maximize the frequency of a memory device, the variations in the pulse width required for a write though data operation and a read operation should be as small as possible. However in current memory devices, the timing of the signals used for write though operations and read operations are subject to variations based on their propagation through largely different signal paths, which can lead to these signals becoming misaligned. As a result, the pulse widths required to be used for the memory devices must be wide enough to ensure that the proper signal is provided on the output of the memory device.